ICM7561/7541/7521 rev. a6 icmic reser ves the right to change specifications without prio r notice 1 12/10/8-bit low power single dac with serial interface and voltage output features ? 12/10/8-bit single dac in 08 lead msop package ? ultra-low power consumption ? guaranteed monotonic ? wide voltage output swing buffer ? three-wire spi/qsp and microwire interface compatible ? three software-selectable power-down output impedances (1 k ohm, 100 k ohm and hi-z) ? schmitt-triggered inputs for direct interfacing to opto-couplers application ? battery-powered applications ? industrial process control ? digital gain and offset adjustment overview the ICM7561, icm7541 and icm7521 are 12-bit, 10-bit and 8-bit voltage output, low power, single dacs respectively, with guaranteed monotonic behavior. t hese dacs are available in 8 lead msop package. they hav e three software-selectable power-down output impedances (1 k ohm, 100 k ohm and hi-z) as additio nal safety feature for applications that drive transduc ers or valves. the operating supply range is 2.7v to 5.5v. the input interface is an easy to use three-wire sp i, qspi and microwire compatible interface. the dac has sch mitt- triggered inputs for direct interfacing to opto-cou plers easily. block diagram input control logic, registers and latches input register refin vo sdi sck ICM7561/7541/7521 cs dac register dac x 2 resistor network power down control ic microsystems ic mic
ICM7561/7541/7521 rev. a6 icmic res erves the right to change specifications without pr ior notice 2 package 0 8 lead m sop v o 1 8 vdd nc 2 7 gnd cs 3 6 ref in sck 4 5 sdi top view pin description (8 lead msop) pin name i/o description 1 vo o dac output voltage 2 nc - no connection 3 cs i active low chip select (cmos) 4 sck i serial clock input (cmos) 5 sdi i serial data input (cmos) 6 refin i reference voltage input 7 gnd i ground 8 vdd i supply voltage
ICM7561/7541/7521 rev. a6 icmic reserv es the right to change specifications without prior notice 3 absolute maximum ratings symbol parameter value unit v dd supply voltage -0.3 to 7.0 v i in input current +/- 25.0 ma v in_ digital input voltage (sck, sdi , clr , cs ) -0.3 to 7.0 v v in_ref reference input voltage -0.3 to 7.0 v t stg storage temperature -65 to +150 o c t sol soldering temperature 300 o c stress greater than those listed under absolute max imum ratings may cause permanent damage to the devi ce. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the o perational sections of this specification is not implied. exposure to absolute maximum rating condit ions for extended periods may affect reliability. ordering information part operating temperature range package ICM7561 -40 o c to 85 o c 08-lead msop icm7541 -40 o c to 85 o c 08-lead msop icm7521 -40 o c to 85 o c 08-lead msop dc electrical characteristics (v dd = 2.7v to 5.5v, v out unloaded; all specifications t min to t max unless otherwise noted) symbol parameter test conditions min typ max unit dc performance ICM7561 n resolution 12 bits dnl differential nonlinearity (notes 1 & 3) 0.4 + 1.0 lsb inl integral nonlinearity (notes 1 & 3) 4.0 + 12.0 lsb icm7541 n resolution 10 bits dnl differential nonlinearity (notes 1 & 3) 0.1 + 1.0 lsb inl integral nonlinearity (notes 1 & 3) 1.0 + 3.0 lsb icm7521 n resolution 8 bits dnl differential nonlinearity (notes 1 & 3) 0.05 + 1.0 lsb inl integral nonlinearity (notes 1 & 3) 0.25 + 0.75 lsb static accuracy ge gain error + 0.5 % of fs oe offset error + 25 mv power requirements v dd supply voltage 2.7 5 5.5 v i dd supply current full scale at vdd=5.5 90 150 ha full scale at vdd=3.6 75 100 ha
ICM7561/7541/7521 rev. a6 icmic res erves the right to change specifications without pr ior notice 4 dc electrical characteristics (continued) (v dd = 2.7v to 5.5v, v out unloaded; all specifications t min to t max unless otherwise noted) symbol parameter test conditions min typ max unit output characteristics vout output voltage range (note 3) 0 v dd v vo sc short circuit current 60 150 ma rout output impedance power-down at 1 k ohm 0.9 1 1.1 ki power-down at 100 k ohm 90 100 110 ki output line regulation v dd =2.7v to 5.5v -3.0 0.4 3.0 mv/v logic inputs v ih digital input high (note 2) 2.4 v v il digital input low (note 2) 0.8 v digital input leakage 5 ac electrical characteristics (v dd = 2.7v to 5.5v, v out unloaded; all specifications t min to t max unless otherwise noted) symbol parameter test conditions min typ max unit sr slew rate 2 v/hs settling time 8 hs mid-scale transition glitch energy 40 nv-s note 1 : linearity is defined from code 110 to 3990 (icm75 61) linearity is defined from code 16 to 1023 (icm7541 ) linearity is defined from code 4 to 255 (icm7521) note 2 : guaranteed by design; not tested in productio n note 3 : see applications information timing characteristics (v dd = 2.7v to 5.5v, all specifications t min to t max unless otherwise noted) symbol parameter test conditions min typ max unit t 1 sck cycle time (note 2) 30 ns t 2 data setup time (note 2) 10 ns t 3 data hold time (note 2) 10 ns t 4 sck falling edge to cs rising edge (note 2) 0 ns t 5 cs falling edge to sck rising edge (note 2) 15 ns t 6 pulse width cs (note 2) 20 ns
ICM7561/7541/7521 rev. a6 icmic reserv es the right to change specifications without prior notice 5 serial interface timing and operation diagram figure 1. serial interface timing diagram figure 2. serial interface operation diagram contents of input shift register device bit control word data word msb lsb ICM7561 12 c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 icm7541 10 c3 c2 c1 c0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a1 a0 icm7521 8 c3 c2 c1 c0 d7 d6 d5 d4 d3 d2 d1 d0 x x a1 a0 figure 3. contents of input shift register cs sdi sck c3 c2 c1 c0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (update output) (enable sck) msb lsb cs sdi sck t 6 t 3 t 2 t 1 t 5 t 4 msb c2 c3 c1 d0 lsb
ICM7561/7541/7521 rev. a6 icmic res erves the right to change specifications without pr ior notice 6 c3 c2 c1 c0 data (d11~d0:7561;d9~d0:7541;d7~d0:7521) function 0 0 0 0 data input loaded into dac, vo updated table 1. serial interface input word control data function c3 c2 c1 c0 d11~d2 d9~d0 d7~d0 d1 a1 a1 d0 (7561) a0 (7541) a0 (7521) 1 1 1 1 x 0 0 dac o/p, wakeup 1 1 1 1 x 0 1 floating output 1 1 1 1 x 1 0 output is terminated with 1kk 1 1 1 1 x 1 1 output is terminated with100 kk table 2. power down mode control detailed description the ICM7561 is a 12-bit voltage output dac. the icm 7541 is the 10-bit version of this family and the icm752 1 is the 8-bit version. these devices have a 16-bit input sh ift register and the dac has a double buffered digital input. this family of dacs has a guaranteed monotonic beha vior. the operating supply range is from 2.7v to 5.5v. reference input the reference input accepts positive dc and ac sign als. the voltage at refin sets the full-scale output vol tage of the dac. the reference input voltage range is from 0 to vdd-1.5v. the impedance at this pin is very high (g reater than 10 m ohm). the dac output amplifier is configu red in a gain of 2 configuration. this means that the full -scale output of the dac will be 2x v ref . to determine the output voltage for any code, use the following equation. v out = 2 x (v ref x (d / (2 n ))) where d is the numeric value of dacs decimal input code, v ref is the reference voltage and n is number of bits, i.e. 12 for ICM7561, 10 for icm7541 and 8 for icm7521. output buffer amplifier the dac has an output amplifier connected in a gain of 2 configuration. this amplifier has a wide output vol tage swing. the actual swing of the output amplifier wil l be limited by offset error and gain error. see the app lications information section for a more detailed discussion. the output amplifier can drive a load of 2.0 k k to v dd or gnd in parallel with a 500 pf load capacitance. the output amplifier has a full-scale typical settl ing time of 8 hs and it dissipates about 100 ha with a 3v suppl y voltage. serial interface and input logic this dac family uses a standard 3-wire connection compatible with spi/qspi and microwire interfaces. data is always loaded in 16-bit words which consist of 4 co ntrol bits (msbs) followed by 12 bits (see figure 3). the ICM7561 uses the last two lsbs of the dac data also for power down control. the icm7541 and icm7521 have th e last 2 lsbs as power down control bits only and the data which gets loaded into the dac register starts at l ocation d0 (see tables 1 and 2). serial data input sdi (serial data input) pin is the data input pin f or the dac. data is clocked in on the falling edge of sck which has a schmitt trigger internally to allow for noise immun ity on the sck pin. this specially eases the use for opto-coup led interfaces. the chip select pin which is the 3 rd pin of 8 lead msop package is active low. this pin frames the input da ta for synchronous loading and must be low when data is be ing clocked into the part. there is an onboard counter on the clock input and after the 16 th clock pulse the data is automatically transferred to a 16-bit input latch a nd the 4 bit control word (c3~c0) is then decoded and the appropriate command is performed depending on the control word (see table 1, 2). chip select pin must be pulled high (level-triggered) and back low for the next data word to be loaded in. this pin also disables the sc k pin internally when pulled high.
ICM7561/7541/7521 rev. a6 icmic reserv es the right to change specifications without prior notice 7 power-down mode the dacs have three software-selectable power-down output impedances (1 k ohm, 100 k ohm and hi-z) as additional safety feature for applications that dri ve transducers or valves. the power down (or wake up command) can be done by loading the control word wi th 1111 (c3 to c0). in power down mode, the selection of the output impedance of the dac is controlled by the la st two bits (d0 and d1 for the ICM7561, or a0 and a1 for t he icm7541/7521). see table 1 and table 2 for details of operation of this function. power-on reset there is a power-on reset on board that will clear the contents of all the latches to all 0s on power-up a nd the dac voltage output will go to ground. applications information power supply bypassing and layout considerations as in any precision circuit, careful consideration has to be given to layout of the supply and ground. the retur n path from the gnd to the supply ground should be short w ith low impedance. using a ground plane would be ideal. the supply should have some bypassing on it. a 10 hf tantalum capacitor in parallel with a 0.1 hf cerami c with a low esr can be used. ideally these would be placed as close as possible to the device. avoid crossing dig ital and analog signals, specially the reference, or running them close to each other. output swing limitations the ideal rail-to-rail dac would swing from gnd to v dd . however, offset and gain error limit this ability. figure 4 illustrates how a negative offset error will affect the output. the output will limit close to ground since this is single supply part, resulting in a dead-band area. as a la rger input is loaded into the dac the output will eventu ally rise above ground. this is why the linearity is specifie d for a starting code greater than zero. figure 5 illustrates how a gain error or positive o ffset error will affect the output when it is close to v dd . a positive gain error or positive offset will cause the output to b e limited to the positive supply voltage resulting in a dead-ban d of codes close to full-scale. deadband negative offset figure 4 . effect of negative offset deadband positive offset offset and gain error v dd figure 5 . effect of gain error and positive offset
ICM7561/7541/7521 rev. a6 icmic res erves the right to change specifications without pr ior notice 8 package information 8 lead msop
ICM7561/7541/7521 rev. a6 icmic reserv es the right to change specifications without prior notice 9 package information icm75x1 p g device 6 - ICM7561 4 - icm7541 2 - icm7521 g = rohs compliant lead - free package . blank = standard package. non lead-free. package m = 8-lead msop
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